hlsfactory.data_packaging

Module Contents

Classes

CompleteHLSData
DataAggregator
ArtifactsXilinx
JSONFileDataAggregator	Shared base for aggregators.
DataAggregatorXilinx
ArtifactAggregator	Aggregator that collects vendor artifacts by file-name pattern.
ArtifactsXLS
DataAggregatorXLS	Google XLS: IR at each stage, RTL, signature/schedule/metrics, options.
ArtifactsCatapult
DataAggregatorCatapult	Siemens Catapult: *.rpt reports and generated RTL.
ArtifactsStratus
DataAggregatorStratus	Cadence Stratus: generated RTL, the BDR report, and metrics/log files.
ArtifactsIntel
DataAggregatorIntel	Intel HLS Compiler (i++) and Quartus: reports, HDL, Quartus reports.
ArtifactsAltera
DataAggregatorAltera	Altera HLS IP Gen and Quartus: reports, interface spec, RTL, logs.
ArtifactsVitisModern
DataAggregatorVitisModern	Config-file Vitis HLS (v++): csynth reports and Verilog/VHDL.

Functions

get_file_in_root

Data

InMemoryArchive
ArtifactCollection

API

hlsfactory.data_packaging.InMemoryArchive = None

class hlsfactory.data_packaging.CompleteHLSData

design: dict | None = None

synthesis: dict | None = None

implementation: dict | None = None

execution: dict | None = None

artifacts: hlsfactory.data_packaging.InMemoryArchive | None = None

design_id: str = 'field(...)'

to_flat_dict() → dict

to_json() → str

to_json_file(file_path: pathlib.Path) → None

to_csv() → str

to_csv_file(file_path: pathlib.Path) → None

class hlsfactory.data_packaging.DataAggregator

Bases: abc.ABC

VENDER = None

abstractmethod gather_hls_design_data(design: hlsfactory.framework.Design) → dict

abstractmethod gather_hls_synthesis_data(design: hlsfactory.framework.Design) → dict

abstractmethod gather_implementation_data(design: hlsfactory.framework.Design) → dict

abstractmethod gather_execution_data(design: hlsfactory.framework.Design) → dict

abstractmethod gather_hls_synthesis_artifacts(design: hlsfactory.framework.Design) → hlsfactory.data_packaging.InMemoryArchive

gather_all_data(design: hlsfactory.framework.Design, **kwargs) → hlsfactory.data_packaging.CompleteHLSData

gather_multiple_designs(designs: list[hlsfactory.framework.Design], n_jobs: int = 1) → list[hlsfactory.data_packaging.CompleteHLSData]

aggregated_data_to_csv(data: list[hlsfactory.data_packaging.CompleteHLSData]) → str

aggregated_data_to_csv_file(data: list[hlsfactory.data_packaging.CompleteHLSData], file_path: pathlib.Path) → None

aggregated_data_to_json(data: list[hlsfactory.data_packaging.CompleteHLSData]) → str

aggregated_data_to_json_file(data: list[hlsfactory.data_packaging.CompleteHLSData], file_path: pathlib.Path) → None

aggregated_data_to_archive(data: list[hlsfactory.data_packaging.CompleteHLSData], file_path: pathlib.Path) → None

hlsfactory.data_packaging.ArtifactCollection = None

class hlsfactory.data_packaging.ArtifactsXilinx(*args, **kwds)

Bases: enum.Enum

IR = 'ir'

ADB = 'adb'

REPORT = 'report'

HDL = 'hdl'

IP = 'ip'

hlsfactory.data_packaging.get_file_in_root(dir_fp: pathlib.Path, file_name: str) → dict

class hlsfactory.data_packaging.JSONFileDataAggregator

Bases: hlsfactory.data_packaging.DataAggregator

Shared base for aggregators.

Every flow writes its results as JSON files in the design directory (data_design.json, data_hls.json, data_implementation.json and execution_data.json), so reading them does not depend on the vendor. Subclasses add the vendor-specific part: collecting the artifacts a flow leaves on disk.

gather_hls_design_data(design: hlsfactory.framework.Design, **_kwargs) → dict

gather_hls_synthesis_data(design: hlsfactory.framework.Design, **_kwargs) → dict

gather_implementation_data(design: hlsfactory.framework.Design, **_kwargs) → dict

gather_execution_data(design: hlsfactory.framework.Design, **_kwargs) → dict

class hlsfactory.data_packaging.DataAggregatorXilinx

Bases: hlsfactory.data_packaging.JSONFileDataAggregator

VENDER = 'Xilinx'

gather_hls_synthesis_artifacts_data(design: hlsfactory.framework.Design, artifacts_to_extract: set[hlsfactory.data_packaging.ArtifactsXilinx] = {ArtifactsXilinx.IR, ArtifactsXilinx.ADB, ArtifactsXilinx.REPORT, ArtifactsXilinx.HDL, ArtifactsXilinx.IP}, error_if_missing_data: bool = False) → hlsfactory.data_packaging.ArtifactCollection

gather_hls_synthesis_artifacts(design: hlsfactory.framework.Design, artifacts_to_extract: set[hlsfactory.data_packaging.ArtifactsXilinx] = {ArtifactsXilinx.IR, ArtifactsXilinx.ADB, ArtifactsXilinx.REPORT, ArtifactsXilinx.HDL, ArtifactsXilinx.IP}, error_if_missing_data: bool = False) → hlsfactory.data_packaging.InMemoryArchive

class hlsfactory.data_packaging.ArtifactAggregator

Bases: hlsfactory.data_packaging.JSONFileDataAggregator

Aggregator that collects vendor artifacts by file-name pattern.

Subclasses declare:

• ARTIFACTS: an enum of artifact kinds (what can be collected).

• ARTIFACT_PATTERNS: for each kind, glob patterns relative to the design directory. Only files are collected.

• SYNTH_FLOW_NAME: the flow whose recorded status in execution_data.json decides whether synthesis completed.

Artifacts are returned as {kind.value: [paths]} and archived as artifacts/<kind>/<path relative to the design directory>.

ARTIFACTS: ClassVar[type[enum.Enum]] = None

ARTIFACT_PATTERNS: ClassVar[dict[enum.Enum, tuple[str, ...]]] = None

SYNTH_FLOW_NAME: ClassVar[str] = None

_synthesis_incomplete(design: hlsfactory.framework.Design) → bool

gather_hls_synthesis_artifacts_data(design: hlsfactory.framework.Design, artifacts_to_extract: collections.abc.Iterable[enum.Enum] | None = None, error_if_missing_data: bool = False) → hlsfactory.data_packaging.ArtifactCollection

Find the requested artifact kinds on disk.

Args:

design: Design whose directory is searched. artifacts_to_extract: Kinds to collect; defaults to every kind. error_if_missing_data: If True, raise FileNotFoundError when a

requested kind matches no files. By default (False) that kind maps to [] and collection continues.

gather_hls_synthesis_artifacts(design: hlsfactory.framework.Design, artifacts_to_extract: collections.abc.Iterable[enum.Enum] | None = None, error_if_missing_data: bool = False, **_kwargs) → hlsfactory.data_packaging.InMemoryArchive

class hlsfactory.data_packaging.ArtifactsXLS(*args, **kwds)

Bases: enum.Enum

IR = 'ir'

RTL = 'rtl'

METRICS = 'metrics'

INTERFACE = 'interface'

OPTIONS = 'options'

SOURCE_MAP = 'source_map'

DEBUG = 'debug'

class hlsfactory.data_packaging.DataAggregatorXLS

Bases: hlsfactory.data_packaging.ArtifactAggregator

Google XLS: IR at each stage, RTL, signature/schedule/metrics, options.

VENDER = 'XLS'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'XLSHLSSynthFlow'

ARTIFACT_PATTERNS = None

class hlsfactory.data_packaging.ArtifactsCatapult(*args, **kwds)

Bases: enum.Enum

REPORT = 'report'

RTL = 'rtl'

class hlsfactory.data_packaging.DataAggregatorCatapult

Bases: hlsfactory.data_packaging.ArtifactAggregator

Siemens Catapult: *.rpt reports and generated RTL.

VENDER = 'Catapult'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'CatapultHLSSynthFlow'

ARTIFACT_PATTERNS = None

class hlsfactory.data_packaging.ArtifactsStratus(*args, **kwds)

Bases: enum.Enum

RTL = 'rtl'

REPORT = 'report'

LOG = 'log'

class hlsfactory.data_packaging.DataAggregatorStratus

Bases: hlsfactory.data_packaging.ArtifactAggregator

Cadence Stratus: generated RTL, the BDR report, and metrics/log files.

VENDER = 'Stratus'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'StratusHLSSynthFlow'

ARTIFACT_PATTERNS = None

class hlsfactory.data_packaging.ArtifactsIntel(*args, **kwds)

Bases: enum.Enum

REPORT = 'report'

HDL = 'hdl'

QUARTUS = 'quartus'

class hlsfactory.data_packaging.DataAggregatorIntel

Bases: hlsfactory.data_packaging.ArtifactAggregator

Intel HLS Compiler (i++) and Quartus: reports, HDL, Quartus reports.

VENDER = 'Intel'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'IntelHLSSynthFlow'

ARTIFACT_PATTERNS = None

class hlsfactory.data_packaging.ArtifactsAltera(*args, **kwds)

Bases: enum.Enum

REPORT = 'report'

INTERFACE = 'interface'

HDL = 'hdl'

LOG = 'log'

class hlsfactory.data_packaging.DataAggregatorAltera

Bases: hlsfactory.data_packaging.ArtifactAggregator

Altera HLS IP Gen and Quartus: reports, interface spec, RTL, logs.

VENDER = 'Altera'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'AlteraHLSSynthFlow'

ARTIFACT_PATTERNS = None

class hlsfactory.data_packaging.ArtifactsVitisModern(*args, **kwds)

Bases: enum.Enum

REPORT = 'report'

HDL = 'hdl'

class hlsfactory.data_packaging.DataAggregatorVitisModern

Bases: hlsfactory.data_packaging.ArtifactAggregator

Config-file Vitis HLS (v++): csynth reports and Verilog/VHDL.

VENDER = 'Xilinx'

ARTIFACTS = None

SYNTH_FLOW_NAME = 'VitisHLSModernSynthFlow'

ARTIFACT_PATTERNS = None