hlsfactory.flow_altera

Altera HLS IP Gen (SYCL/ahls) synthesis, emulation, RTL simulation and Quartus.

Module Contents

Classes

AlteraHLSSynthData
AlteraHLSDesign
AlteraImplDesignResource	Quartus fitter results, retaining each kernel/system row and clock.
_AlteraFlow
AlteraHLSSynthFlow	Generate RTL IP, optimization reports and estimated resource metrics.
AlteraHLSCsimFlow	Compile and run the SYCL host testbench on the FPGA emulator.
AlteraQuartusImplFlow	Compile a hardware device image through Quartus; requires Quartus licensing.
AlteraHLSCosimFlow	Compile and run the host testbench against RTL in Questa.

Functions

read_altera_report

Read the objects in a 2026 HLS IP Gen NDJSON report.

Data

HLSFACTORY_ALTERA_HLS_PATH_ENV_VAR
HLSFACTORY_ALTERA_QUESTA_SETUP_ENV_VAR
_QUESTA_INI_COMPAT_SCRIPT

API

hlsfactory.flow_altera.HLSFACTORY_ALTERA_HLS_PATH_ENV_VAR = 'HLSFACTORY_ALTERA_HLS_PATH'

hlsfactory.flow_altera.HLSFACTORY_ALTERA_QUESTA_SETUP_ENV_VAR = 'HLSFACTORY_ALTERA_QUESTA_SETUP'

hlsfactory.flow_altera._QUESTA_INI_COMPAT_SCRIPT = <Multiline-String>

hlsfactory.flow_altera.read_altera_report(path: pathlib.Path) → list[dict[str, Any]]

Read the objects in a 2026 HLS IP Gen NDJSON report.

class hlsfactory.flow_altera.AlteraHLSSynthData

resources_ALUTs_used: int = None

resources_FFs_used: int = None

resources_RAMs_used: int = None

resources_DSPs_used: int = None

resources_MLABs_used: int = None

resources_ALUTs_avail: int = None

resources_FFs_avail: int = None

resources_RAMs_avail: int = None

resources_DSPs_avail: int = None

resources_MLABs_avail: int = None

classmethod parse_from_synth_report_file(data_file: pathlib.Path) → hlsfactory.flow_altera.AlteraHLSSynthData

class hlsfactory.flow_altera.AlteraHLSDesign

name: str = None

target_clock: str | None = None

family: str = None

product: str = None

quartus: str = None

time: str = None

version: str = None

kernels: list[str] = None

classmethod parse_from_synth_report_file(info_json: pathlib.Path, summary_json: pathlib.Path) → hlsfactory.flow_altera.AlteraHLSDesign

class hlsfactory.flow_altera.AlteraImplDesignResource

Quartus fitter results, retaining each kernel/system row and clock.

resource_usage: list[dict[str, Any]] = None

clock_frequencies: list[dict[str, Any]] = None

classmethod parse_from_impl_report_file(quartus_json: pathlib.Path) → hlsfactory.flow_altera.AlteraImplDesignResource

class hlsfactory.flow_altera._AlteraFlow(ahls_bin: str | pathlib.Path | None = None, altera_install_dir: str | pathlib.Path | None = None, ahls_sh: str | pathlib.Path | None = None, log_output: bool = False, log_execution_time: bool = True)

Bases: hlsfactory.framework.ToolFlow

flow_name: hlsfactory.design_config.FlowName = None

stage: str = None

result_file: str = None

questa_setup_script: pathlib.Path | None = None

execute(design: hlsfactory.framework.Design, timeout: float | None = None) → list[hlsfactory.framework.Design]

_collect_results(design_dir: pathlib.Path, output: pathlib.Path, clock: str | None) → None

class hlsfactory.flow_altera.AlteraHLSSynthFlow(ahls_bin: str | pathlib.Path | None = None, altera_install_dir: str | pathlib.Path | None = None, ahls_sh: str | pathlib.Path | None = None, log_output: bool = False, log_execution_time: bool = True)

Bases: hlsfactory.flow_altera._AlteraFlow

Generate RTL IP, optimization reports and estimated resource metrics.

Initialization

Use an initialized native environment or the installer’s container.

Explicit compiler/launcher arguments take precedence. Otherwise resolve altera_install_dir, HLSFACTORY_ALTERA_HLS_PATH, then PATH. Native installations must have their vendor environment initialized.

name = 'AlteraHLSSynthFlow'

flow_name = None

stage = 'synth'

result_file = 'data_altera_synth.json'

class hlsfactory.flow_altera.AlteraHLSCsimFlow(ahls_bin: str | pathlib.Path | None = None, altera_install_dir: str | pathlib.Path | None = None, ahls_sh: str | pathlib.Path | None = None, log_output: bool = False, log_execution_time: bool = True)

Bases: hlsfactory.flow_altera._AlteraFlow

Compile and run the SYCL host testbench on the FPGA emulator.

Initialization

Use an initialized native environment or the installer’s container.

Explicit compiler/launcher arguments take precedence. Otherwise resolve altera_install_dir, HLSFACTORY_ALTERA_HLS_PATH, then PATH. Native installations must have their vendor environment initialized.

name = 'AlteraHLSCsimFlow'

flow_name = None

stage = 'csim'

result_file = 'data_altera_csim.json'

class hlsfactory.flow_altera.AlteraQuartusImplFlow(ahls_bin: str | pathlib.Path | None = None, altera_install_dir: str | pathlib.Path | None = None, ahls_sh: str | pathlib.Path | None = None, log_output: bool = False, log_execution_time: bool = True)

Bases: hlsfactory.flow_altera._AlteraFlow

Compile a hardware device image through Quartus; requires Quartus licensing.

Initialization

Use an initialized native environment or the installer’s container.

Explicit compiler/launcher arguments take precedence. Otherwise resolve altera_install_dir, HLSFACTORY_ALTERA_HLS_PATH, then PATH. Native installations must have their vendor environment initialized.

name = 'AlteraQuartusImplFlow'

flow_name = None

stage = 'impl'

result_file = 'data_altera_impl.json'

class hlsfactory.flow_altera.AlteraHLSCosimFlow(ahls_bin: str | pathlib.Path | None = None, altera_install_dir: str | pathlib.Path | None = None, ahls_sh: str | pathlib.Path | None = None, log_output: bool = False, log_execution_time: bool = True, questa_setup_script: str | pathlib.Path | None = None)

Bases: hlsfactory.flow_altera._AlteraFlow

Compile and run the host testbench against RTL in Questa.

Initialization

Optionally source a trusted Bash simulator setup after vendor setup.

The script configures PATH and licensing for both compilation and runtime. It must be accessible at the same absolute path inside the container.

name = 'AlteraHLSCosimFlow'

flow_name = None

stage = 'cosim'

result_file = 'data_altera_cosim.json'